1. Field of the Invention
The present invention relates generally to manufacture of semiconductor devices incorporating a metal interconnect. More specifically, it relates to a composition and process to clean post etch residues at an interconnect level, such as with a copper metallurgy, preferably incorporating a damascene/dual damascene structure. The invention further relates to a composition for other post etch residue-cleaning applications, such as aluminum, or aluminum alloy interconnects with misaligned tungsten plugs.
A key challenge in reduced geometry devices, such as 0.18 μm technology, is the interconnect RC delay time, which becomes the limiting factor of the device performance. This delay can be improved by combining low dielectric constant between tracks and the use of copper as a better conductor. This application is directed to solving some of the difficulties in integrating this type of interconnects, and a new strategy for the post dielectric etch cleaning process. The development of new cleaning chemistries and processes for their use, which are compatible with copper and low-k dielectric materials, is essential for process integration.
Since copper can not easily be dry etched, the use of damascene or dual damascene structures is becoming a key solution to realize this integration. With the appearance of new materials such as organic polymers for inter metal dielectric material, and the need to etch complex layers of dielectric materials, photoresist removal and cleaning steps require a new strategic approach.
2. Description of the Prior Art
During the fabrication of microcircuits, photoresist material is used to pattern, and transfer patterns onto the appropriate material. For example at interconnect levels the appropriate material will be either metal for electrically conducting paths or dielectric for isolating material in-between the conducting lines. Traditional interconnects are made of aluminum or aluminum alloys isolated by dielectric material, for example silicon dioxide.
More recently developed interconnects use copper as the conducting material and low-k dielectric material (a dielectric, having a dielectric constant ∈ smaller than the dielectric constant of silicon dioxide). FIGS. 1 and 2 show a typical structure used in this case. To integrate copper and eventually aluminum, the pattern is transferred from the photoresist (3) through the dielectric (2). The gaps are then filled up by the conducting layer. This process is called damascene and can integrate either one level of interconnect only (single damascene) or both the horizontal interconnects and the vertical interconnects called vias (dual damascene). Vias always open atop the underlying metal lines (1) and good cleanliness of the via is required in order to minimize electrical resistance along the interconnect.
Various processes have been developed to build those structures, as disclosed, for example, in U.S. Pat. Nos. 5,739,579; 5,635,423; 5,705,430 and 5,686,354, which can include optional layers into the dielectric stack (5,6) but all those processes have in common:    that the via needs to be cleaned from all post etch residues (7 and 8 ), without damaging the metal, before the second metal layer can be deposited,    that the whole dielectric material needs to be cleaned from copper compounds back-sputtered onto the sidewall and top surface (8) on the underlying copper during the final part of the etching, called “opening”.    that the transfer of the wafer from the etching chamber to the ambient air for further processing creates oxidized copper compounds CuO or Cu2O that need to be cleaned to minimize the via resistance. IC manufacturing requires an excellent cleaning of copper residues, as copper diffuses very easily into silicon dioxide and other dielectric materials ultimately risking the creation of a failure (“killing” the device).
It has been described previously to clean materials used in the semiconductor industry by including a small amount (generally between 1% and 5% weight) of choline and other compounds to remove or avoid adsorption of metal impurities (U.S. Pat. Nos. 4,239,661, 4,339,340, PAJ 6,163,495, PAJ 6,041,773, PAJ 2,275,631, PAJ 1,191,450). Choline base is also well known for its use as developer of positive working photoresist (U.S. Pat. Nos. 4,294,911, 4,464,461). It has also been recognized that choline base can act as a etching agent of metal for thin film layer definition (PAJ 62,281,332, U.S. Pat. No.4,172,005) and that adding choline atoms into an etching chamber when etching copper helps to lower the process temperature and hence minimize copper oxidation. U.S. Pat. No. 5,846,695 discloses aqueous solutions of quaternary ammonium hydroxides, including choline, in combination with nucleophilic amines and sugar and/or sugar alcohols, for removal of photoresist and photoresist residues in integrated circuit fabrication.
The present invention is aimed at cleaning residues left after etching dielectric material and openings on a copper layer. Those residues can be minimal if the main etching residues and photoresist are cleaned before the final step of forming openings on copper, in which case we are dealing with residues due to the “opening” etch step only, e.g. copper rich residues on the bottom of the openings and copper back sputtered onto the dielectric material surfaces. But the residues become more complex if the “opening” etch is done directly after the main etch, in which case the post etch treatment is required to clean main etch residues (containing CFx, CHFx . . . ), to clean the bottom residues (containing Cu, CuO, Cu02), as well as the back sputtered copper. Additionally it is required that the post etch treatment remove photoresist.
Existing cleaning compositions used in the semiconductor industry are not suitable for the following reasons:    amine containing products are not compatible with copper and dissolve the metal at the exposed areas;    dilute hydrofluoric acid solutions (DHF) remove the sidewall polymer and CuO compounds by aggressively attacking the sidewall of the dielectric and hence change the designed dimensions of the device. Furthermore those solutions are ineffective for cleaning Cu2O or CFx compounds.
Optionally the photoresist might or might not be removed before the copper is exposed. Using traditional photoresist removal techniques is not ideal for the following reasons:    an oxygen plasma step will oxidize the copper to the CuO and Cu20 states, which will increase the via resistance,    an oxygen plasma step will be detrimental to organic dielectric material, if used, by etching the material in an uncontrolled manner.    a traditional solvent used to remove photoresist such as, for example, products containing N-methyl pyrrolidone might require an extra cure step to recover the dielectric constant and properties of an organic dielectric.
The demand for faster devices has driven down the scale of the design rules. Today's 0.18 μm technology is reaching hole dimensions of 0.25 μm. Since the introduction of 0.25 μm technology we have seen that interconnects are becoming the limiting speed factor of the device due to interconnect resistivity as well as the RC delay induced by adjacent interconnects. A solution for lower resistance of the interconnects is to switch the interconnect metal from aluminum to copper.
Similarly, a solution for reduced capacitance between adjacent metal lines is to decrease the dielectric constant of the material in-between the lines. This can be achieved by the use of emerging new low-k materials.
Copper has been chosen because it is a relatively inexpensive metal with better conductivity(ρ=1.7 Ω.cm) than aluminum (ρ=2.7 Ω.cm). However the main drawbacks of this material are first its high diffusivity into silicon, introducing risk of a killing defect in the front end device, and second the difficulty to dry etch it and integrate it in traditional processes. In addition, copper does not form an oxide passivation layer under ambient conditions (as aluminum does), making this metal very difficult to work with.
On the gap-fill side, the industry s choice of low-k dielectric material has not yet emerged, though various candidates have been suggested. It has been shown that a general trend to achieve lower dielectric constant is to use material with less silicon and more carbon. There is then a logical evolution from the inorganic materials (such as SiO2[∈=4], SiOF [∈=3.5]) to silsesquioxane types of material (such as HSQ, MSQ [3.0<∈<3.5]), towards organic material, such as benzyl cyclobutane (BCB) or silicon low k (SiLK) [∈=2.7]), with the ultimate low-k value being reached with air gaps.
The SIA Roadmap predicted the merging of the work done on the one hand with copper integration, and on the other hand with low-k materials, by the end of 1998. The strategy chosen here is the introduction of copper first followed by the transfer of the process to low-k material. However both projects are progressing together and a cleaning strategy has to be developed at this stage, taking into account the requirements of all the materials that will be used in the final process.
We have seen over the past few years, the emergence of the damascene type of structure in which the design is etched into a dielectric layer, which is then filled with conducting wires and planarized (FIG. 1). Dual damascene structures have the advantage of incorporating both lines and vias in one deposition step; this reduces the number of process steps and is therefore cost effective. However the main reason for the emergence of such structures nowadays is the fact that this is the easiest way to introduce copper.
Variations of the dual damascene structure exist, incorporating a series of layers for process purposes such as anti-reflective coatings, adhesion promoters, moisture barriers, diffusion barriers, polishing stops, buried etch mask and so on. The choice of whether those have to be used or not and what material (SiOxNy or Six Ny) should be used for them often depend upon the final choice of the low-k material.